Partition and propagate: an error derivation algorithm for the design of approximate circuits

Inexact hardware design techniques have become popular in error-tolerant systems, where energy efficiency is a primary concern. Several techniques aim to identify circuit portions that can be discarded under an error constraint, but research on systematic methods to determine such error is still at an early stage. We herein illustrate a generic, scalable algorithm that determines the influence of each circuit gate on the final output. The algorithm first partitions the graph representing the circuit, then determines the error propagation model of the resulting subgraphs. When applied to existing approximate design frameworks, our solution improves their efficiency and result quality

Embedded system design specification: merging reactive control and data computation

We have presented two language extensions for C and Java for embedded system specification, simulation and implementation. The two languages JESTER and ECL build upon the ESTEREL synchronous semantic foundation that provides support for waiting, concurrency and preemption. They nicely support specification of mixed control/data modules. The compilation is performed by splitting the source code into reactive ESTEREL code (as large as possible, in the current implementation) and data-dominated C or Java code. The large reactive portion can be robustly optimized and synthesized to either hardware or software, while the C residual code must be either implemented in software as is or the user must provide a a hardware implementation

Incremental FSM Re-encoding for Simplifying Verification by Symbolic Traversal

State space exploration of finite state machines is used to prove properties about sequential behavior, such as the equivalence of two machines. The three paradigms for exploring reachable states, forward traversal, backward traversal and a combination of the two, reach their limits on large practical examples. Approximate techniques and combinational verification are far less expensive but these imply sufficient, not strictly necessary conditions. Extending the applicability of the purely combinational check to pairs of machines with different encodings can be achieved through state minimization, partitioning, and re-encoding the FSMs to factor out their differences. This paper focuses on re-encoding: we present an incremental approach to re-encoding for sequential verification. We transform the product machine traversal to a combinational verification in the best case, and to a computationally simpler product machine traversal in the general case. Experimental results demonstrating the effectiveness of these techniques o medium-large circuits where other techniques may fail